With the recent increase of integration density of a DRAM, a cell size and an area to be occupied by a capacitor of the DRAM cell tend to reduce, respectively. In order to keep a capacitance of such capacitor at an acceptable value, a stacked capacitor has been used since it can provide a large capacitor area therein and it is capable of reducing interference between DRAM cells.
FIG. 1A to FIG. 1C are flow diagrams showing the process steps of a prior art method for fabricating a DRAM cell capacitor. FIG. 1A illustrates, in cross-section, a portion of a semiconductor substrate 10 having already undergone several process steps. Briefly, a device isolation layer 12 is formed on the semiconductor substrate 10 to define active and inactive regions. A gate electrode structure 14 is formed over the semiconductor substrate 10. The gate electrode structure 14 is constituted by a gate oxide layer, a gate electrode, and a passivation layer. A source/drain region 16 is formed in the semiconductor substrate 10 adjacent to the gate electrode structure 14. An oxide layer 18 is formed over the semiconductor substrate 10 including the gate electrode structure 14. A storage contact hole 20 is opened in the oxide layer 18 to the source/drain region 16 and filled with a conductive material to form a storage contact plug 22. A polysilicon layer 24 is deposited on the contact plug 22 and over the oxide layer 18 to a thickness of about 10,000.ANG.. A photoresist layer is spin coated over the polysilicon layer 24 and is patterned into desired configuration 26 using conventional photolithographic process.
The polysilicon layer 24 exposed by the patterned photoresist layer 26 is etched using poly etch-back process to form a storage node 24a as shown in FIG. 1B. After that, the patterned photoresist layer 26 is removed through ashing and stripping as shown in FIG. 1C.
However, the process of etching such tall as 10,000.ANG. thick polysilicon is generally carried out under conditions that targets the etching process of 13,000.ANG. to 15,000.ANG. polysilicon layer. Accordingly, over-etching is inevitably performed. Due to this overetching process, the storage node 24a interfacing the oxide layer 18 and contact plug 22 are subject to over etching.
FIG. 2 is cross-sectional view of a conventional DRAM cell capacitor fabricated by above-mentioned method in case of misalignment. Referring to FIG. 2, if misalignment between the storage node 24a and the contact plug 22 occurs, bottom edges of the storage node 24a facing the contact plug 22 are severely over-etched(which is depicted as inside the dotted circle) and thereby forming a trench pit(a) which reduces contact area between the storage node 24a and contact plug 22 as shown in FIG. 2. As a result, the storage node 24a is subjected to be easily separated from underlying contact plug 22 electrically due to this trench pit(a). Furthermore, the storage node 24a is subjected to falling down during subsequent cleaning process thereby to cause short between DRAM cells.